1. Field of the Invention
The present invention relates to a circuit design, and more particularly, to a circuit design for detecting and preventing setup fails.
2. Description of the Related Art
In circuit design, it is not uncommon for the chip to fail during the test stage. Therefore, debugging, i.e. locating the problem that causes the chip to fail, is extremely important, and may even comprise a majority of the time to produce the product. Setup fail is one of the most troublesome and significant issues related to chip production.
FIG. 1 shows a conventional circuit block. As shown in FIG. 1, the circuit block 100 comprises a first latch 102 and a second latch 104. The first latch 102 receives a data signal A and a clock signal CLK1, and outputs a data signal B. The second latch 104 receives the data signal B, which passes through a combinational logic 150, and a clock signal CLK2, and outputs a data signal Y. Normally, the data signal B arrives at the second latch 104 before the clock signal CLK2. Therefore, the data signal B is correctly latched, and is outputted as the data signal Y. However, if the data signal B arrives at the second latch 104 after the clock signal CLK2, the data signal B cannot be correctly latched by the second latch 104, and a setup fail occurs.
Debugging setup fails on chips can be very costly and time consuming, especially if there are no probe pads available when they are needed in the debugging process. Therefore, there is a need to design a circuit and method to detect and prevent setup fails.